The electrical circuitry of electronic components such as image display devices and touch screen devices can be manufactured by different methods. Said electrical circuitry most often comprises copper or a copper alloy due to the high electrical conductivity of said materials.
Such electrical circuitry can be for example manufactured by physical vapour deposition methods (PVD) such as sputtering or chemical vapour deposition methods (CVD) wherein copper or a copper alloy is deposited onto a dielectric substrate. Optionally, an adhesion layer, for example a layer of titanium, molybdenum or a multilayer stack comprising a titanium layer and a molybdenum layer is first deposited onto the substrate followed by depositing the copper or a copper alloy which is the main contributor of the electrical circuitry.
In another method for depositing an electrical circuitry onto a dielectric substrate in the manufacture of electronic components such as image display devices and touch screen devices, the electrical circuitry is deposited by electroless plating of copper or a copper alloy onto a substrate which is activated with a noble metal. Such an electroless (autocatalytic) plating method onto substrates activated with a noble metal is disclosed in EP 2 524 976 A1.
The electrical circuitry of electronic components such as image display devices and touch screen devices can also be manufactured by an additive method wherein a catalytic ink is deposited onto a dielectric substrate material such as polyethylene terephthalate (PET) foils and cured thereafter. The cured catalytic ink is then used as a plating base for electroless (autocatalytic) plating of copper and copper alloys thereon. Such additional copper or copper alloy layer(s) are necessary in order to obtain the required electrical conductivity for the circuitry pattern which is usually not obtained by the cured catalytic ink alone. A method for electroless plating of metals and metal alloys such as copper and copper alloys onto cured catalytic inks is for example disclosed in EP 13188464.5.
In still another manufacturing method, an electrical circuitry is deposited by electroplating copper or a copper alloy onto an electrically conductive pattern or layer attached to the dielectric substrate.
One disadvantage of such copper or copper circuitry independent of the method used to deposit copper or a copper alloy onto the substrate is the strong optical reflectivity of the shiny surface which leads to an optical visibility of said circuitry despite a very narrow circuitry line width of e.g. 50 μm, 20 μm, 10 μm and less, and proprietary circuitry pattern geometries such as rectangular or hexagonal grids used for image display devices and touch screen devices.
Different methods for reducing the optical reflectivity of copper and copper alloy surfaces in the manufacture of electronic components such as image display devices and touch screen devices are known in the art.
A blackening procedure for copper circuitry in the manufacture of electronic components such as touch screen devices is disclosed in US 2013/0162547 A1 wherein the copper surface is chemically oxidized to brown Cu2O and black CuO. Thereby, the optical reflection of the copper circuitry surface is reduced.
Another chemical oxidation procedure for copper circuitry in the manufacture of electronic components such as touch screen devices is disclosed in US 2014/0057045 A1. The copper surface is treated with chemical substances such as selenium compounds, sulfate compounds or triazole compounds in order to obtain a darkened copper surface and thereby reducing the optical reflectivity of the copper circuitry.
A method for reducing the optical reflectivity of a circuitry made of silver is disclosed in U.S. Pat. No. 7,985,527 B2. Silver is first blackened by a chemical oxidation treatment and then the black silver oxides formed are stabilized by contacting said silver oxides with a solution comprising either palladium ions or metallic palladium.
A disadvantage of such chemical oxidation treatments disclosed in the prior art is the weak mechanical stability of such surface oxide layers which are brittle and have a low adhesion to the underlying copper or silver surface. Accordingly, such blackened circuitry lacks reliability.
Another disadvantage of such chemical oxidation treatments is that copper of the circuitry lines is consumed during formation of copper oxides. Accordingly, portions of the initial copper circuitry are converted into electrically non-conductive copper oxides and the specific resistivity of said copper circuitry is increased after formation of copper oxides.
EP 0 926 263 A2 relates to a process for bonding resin-layers to a roughened copper foil in order to form a multilayer printed circuit board. The process involves microetching said copper foil and thereafter contacting the copper foil with an adhesion promoting composition comprising a reducing agent and a metal selected from the group consisting of gold, silver, palladium, ruthenium, rhodium, zinc, nickel, cobalt, iron and alloys of the foregoing metals. In one embodiment, an immersion-type palladium solution is used as the adhesion promoting layer in conjunction with the micro etching solution. The method does not relate to the formation of circuitry. The purpose of the treatment is provide a roughened copper foil which is thereafter laminated to a resinous layer. The method according to EP 0 926 263 A2 results in formation of a multilayer circuit board. It does not disclose manufacturing of copper circuitry suitable for image display devices and touch screens. US 2008/0224314 A1 discloses formation of a cap layer onto copper interconnect surfaces. The cap layer (see paragraph [0003]) can be Ni, Ni(P), Ni(Co) or Co(P). The cap layer serves to form a diffusion barrier and corrosion prevention layer on inlaid copper features, paragraph [0003]. It is suggested to deposit an “activation layer” such as palladium onto the surface of the copper interconnect which serves to promote subsequent deposition of another metal. US 2008/0224314 A1 does not disclose formation of a copper or copper alloy circuitry having deposited thereon a palladium or palladium alloy as the outermost layer.